library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mux21 is
port(	A : in   std_logic;
		B : in   std_logic;
		S : in   std_logic;
		O : out std_logic
);
end mux21;

architecture Structural of mux21 is
begin

	O <= (A and not(S)) or (B and S);

end Structural;

